@``ME@
Email: <alexander.samoilov AT google DOT com>
...
Literate Programming Org-mode, blog et al.
http://en.wikipedia.org/wiki/Org-mode
Org-mode
http://orgmode.org/worg/org-contrib/babel/
http://praveen.kumar.in/2012/03/10/org-mode-latex-and-minted-syntax-highlighting/
https://github.com/jceb/vim-orgmode/
http://orgmode.org/worg/exporters/beamer/tutorial.html
http://www.howardism.org/Technical/LP/Introduction.html
<b>Org mode batch execution</b>
from
http://orgmode.org/manual/Batch-execution.html
It is possible to call functions from the command line. This shell script calls org-babel-tangle on every one of its arguments.
Be sure to adjust the paths to fit your system.
<pre>
- #!/bin/sh # -*- mode: shell-script -*- # # tangle files with org-mode #
DIR=pwd FILES="" # wrap each argument in the code required to call tangle on it for i in $@; do
- FILES="$FILES \"$i\""
- (find-file (expand-file-name file \"$DIR\")) (org-babel-tangle)
(kill-buffer)) '($FILES)))" 2>&1 |grep tangled
</pre>
<b>Emacs evil-mode -- vim emulation inside Emacs</b>
https://antono.info/rus/2011/9/evil-mode
======<b>orgmode for Sublime Text 2 & 3</b> ======
https://github.com/danielmagnussons/orgmode
http://danielmagnusson.com/orgmode-for-sublime-text
http://kieranhealy.org/files/misc/workflow-apps.pdf
https://github.com/kjhealy/workflow-paper
======<b>Beamer presentation in orgmode</b> ======
http://orgmode.org/worg/exporters/beamer/presentation.html
Etc
http://en.wikipedia.org/wiki/Comparison_of_notetaking_software
Lightweight markup language
http://en.wikipedia.org/wiki/Lightweight_markup_language
http://en.wikipedia.org/wiki/Markdown <b>Markdown</b> is a lightweight markup language
http://en.wikipedia.org/wiki/Comparison
ARM docs
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0059a/index.html
<b>Architecture Simulators</b>
GPGPU
GPGPU+m5sim
http://cpu-gpu-sim.ece.wisc.edu/
http://homepages.cae.wisc.edu/~wangh/
SimpleScalar LLC
http://www.ecs.umass.edu/ece/koren/architecture/Simplescalar/SimpleScalar_introduction.htm
Todd Austin
http://web.eecs.umich.edu/~taustin/
* is the author of SimpleScalar * Professor, EECS, University of Michigan * director of Center for Future Architectures Research (C-FAR)
Ocelot+macsim
http://code.google.com/p/gpuocelot/
http://code.google.com/p/macsim/
MVT
http://staff.cs.utu.fi/research/MOTH/papers/mvt-simulator.pdf
http://staff.cs.utu.fi/research/MOTH/
SMAsim
http://www.iaeng.org/publication/WCE2010/WCE2010_pp509-514.pdf
see MVT
The MV5 Simulator
* An Event-driven, Cycle-accurate Simulator for Heterogeneous Manycore Architectures
https://sites.google.com/site/mv5sim/
* from here
http://www.cs.virginia.edu/~skadron/
Multi2Sim A CPU-GPU Simulator for Heterogeneous Computing
GEM5 ARM
http://www.m5sim.org/CPU_Models
For detailed information about building the simulator and getting started please refer to:
* The main website: http://www.gem5.org
* Documentation wiki: http://www.gem5.org/Documentation
* Doxygen generated: http://www.gem5.org/docs
* Tutorials: http://www.gem5.org/Tutorials
Specific pages of interest are:
http://www.gem5.org/Introduction
http://www.gem5.org/Build_System
http://www.gem5.org/Dependencies
http://www.gem5.org/Running_gem5
see also
http://www.m5sim.org/Publications
Chisel and RISC-V
https://chisel.eecs.berkeley.edu/
http://riscv.eecs.berkeley.edu/
===== Getting started =====
Dubbed from here:
https://github.com/ucb-bar/chisel/
<pre> To start working on a circuit with Chisel, first create a project directory with a standard Scala/SBT layout.
$ mkdir -p chisel-hello/src/main/scala $ cd chisel-hello Insure that your build.sbt contains a reference to Scala version greater or equal to 2.10 and add a dependency on the Chisel library.
$ diff -u prev build.sbt +scalaVersion := "2.10.2" +libraryDependencies += "edu.berkeley.cs" %% "chisel" % "2.0-SNAPSHOT"
Edit the source files for your circuit
$ cat src/main/scala/Hello.scala import Chisel._
class HelloModule extends Module {
- val io = new Bundle {} printf("Hello World!\n")
}
class HelloModuleTests(c: HelloModule) extends Tester(c, Array(c.io)) {
- defTests {
- true
}
object hello {
- def main(args: Array[String]): Unit = {
- chiselMainTest(Array[String]("--backend", "c", "--genHarness"),
() => Module(new HelloModule())){c => new HelloModuleTests(c)}
- chiselMainTest(Array[String]("--backend", "c", "--genHarness"),
}
Execute sbt run to generate the C++ simulation source for your circuit
$ sbt run Compile the resulting C++ output to generate a simulation executable
$ g++ -std=c++11 -o HelloModule HelloModule.cpp HelloModule-emulator.cpp Run the simulation executable for one clock cycle to generate a simulation trace
$ ./HelloModule 1 Hello World! </pre>
More elaborate Chisel use-cases
* https://github.com/schoeberl/comphdl.git
* patmos processor -- look for cache implementation in Chisel
https://github.com/t-crest/patmos
and
https://github.com/t-crest/patmos.git
see also
and for TMS320C64X
See also
http://www.eecs.berkeley.edu/~yunsup/
http://inst.eecs.berkeley.edu/~cs152/sp13/
https://github.com/danluu/sodor
https://github.com/danluu?tab=repositories
ptarm - Precision Timed ARM
http://chess.eecs.berkeley.edu/pret/src/ptarm-1.0/ptarm_simulator.html
Oleg Strikov's review:
<pre>
Я по диагонали просмотрел исходники. Как я понял, симулятор не поддерживает full-system simulation (загрузку ОС,), а может только запускать бинарники и эмулировать системные вызовы. Это делает его практически не применимым для симуляции high-end железа где важно именно взаимодействие компонентов ОС (бразуер загрузить, например). Для какого-нибудь глубокого embedded'а (буз ОС) может пригодиться, но я не вижу причин не использовать вместо него gem5 и там и там.
Кроме того симулятор поддерживает только систему команд ARMv4 (это только ARM-mode, без Thumb/Thumb2 и NEON). Поэтому даже в этом направлении еще пилить и пилить.
В итоге -- это приличный учебный/курсовой проект на тему как писать симуляторы. Но не думаю, что нечто большее. С другой стороны я не слышал чтобы в МГУ/МФТИ/МИФИ/МГТУ делали нечто подобное. Поэтому респект.
Олег
</pre>
misc - RSIM simulator circa 1997
http://rsim.cs.illinois.edu/distribution/
Historical - CMS
http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/VM_370/plm/
==== Verilog simulators + Verilog-to-Route ====
* http://en.wikipedia.org/wiki/List_of_Verilog_simulators
* The Verilog-to-Routing (VTR) Project for FPGAs https://code.google.com/p/vtr-verilog-to-routing/
* Qflow 1.0: An Open-Source Digital Synthesis Flow http://opencircuitdesign.com/qflow/welcome.html http://opencircuitdesign.com/verilog/
* Xilinx ISE
SystemC
http://www.accellera.org/downloads/standards/systemc
LEF/DEF
https://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=84
Free 45nm Nangate cell library
https://www.si2.org/openeda.si2.org/projects/nangatelib
Drawing vectorized digital logic circuits
<b>Graphics Layout Engine</b>
* http://glx.sourceforge.net/subroutines/electronics.html http://glx.sourceforge.net/index.html
* http://tex.stackexchange.com/questions/13645/drawing-vectorized-digital-logic-circuits?lq=1
* https://ece.uwaterloo.ca/~aplevich/Circuit_macros/html/examples.html
https://ece.uwaterloo.ca/~aplevich/Circuit_macros/
* http://ci.louisville.edu/tom/software/LaTeX/mpcirc/
From here:
http://tex.stackexchange.com/questions/3565/electric-circuits-in-tex-latex-and-friends
github architecture/processor simulator projects
* Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
https://github.com/ayzk/Simulator_CPU
* The OpenRISC 1000 architectural simulator
https://github.com/openrisc/or1ksim
* MARSS-x86 : Micro-Architecture & System Simulator for x86
https://github.com/binghamton/marss
* tiny project: HPCA - Simulator which simulates the processor, cache, DRAM, branch predictors, virtual memory and simultaneous multithreading
https://github.com/n3nash/architecture-simulator
* another tiny processor simulator with pipelining and caching
https://github.com/mschartman/ProcessorSimulator
* Educational load/store instruction set architecture processor simulator; maybe not very useful
https://github.com/dwelch67/lsasim
* Nobody knows what this is.
https://github.com/puppeh/chipmunk
* Cache simulator in haskell
https://github.com/itkovian/CacheSim
University Courses on Processor Architecture
http://pages.cs.wisc.edu/~david/courses/cs552/S12/includes/cache-sim.html
http://pages.cs.wisc.edu/~david/courses/cs552/S12/includes/cache-mod.html
http://pages.cs.wisc.edu/~david/courses/cs552/S12/includes/four_bank_mem.html
https://www.cis.upenn.edu/~milom/cis371-Spring13/lab/lab3/
http://www.cis.upenn.edu/~milom/
http://inst.eecs.berkeley.edu/~cs150/sp11/agenda/lec/lec12-proj3.pdf
http://inst.eecs.berkeley.edu/~cs150/sp11/agenda/
see also
http://readler.com/Verilog.html
http://www.asic-world.com/examples/verilog/